diff --git a/drivers/serial/serial_stm32.h b/drivers/serial/serial_stm32.h
index d08ba1f..42fb132 100644
--- a/drivers/serial/serial_stm32.h
+++ b/drivers/serial/serial_stm32.h
@@ -12,6 +12,8 @@
 #define CR3_OFFSET(x)	(x ? 0x14 : 0x08)
 #define BRR_OFFSET(x)	(x ? 0x08 : 0x0c)
 #define ISR_OFFSET(x)	(x ? 0x00 : 0x1c)
+
+#define ICR_OFFSET	0x20
 /*
  * STM32F4 has one Data Register (DR) for received or transmitted
  * data, so map Receive Data Register (RDR) and Transmit Data
@@ -23,28 +25,24 @@
 struct stm32_uart_info {
 	u8 uart_enable_bit;	/* UART_CR1_UE */
 	bool stm32f4;		/* true for STM32F4, false otherwise */
-	bool has_overrun_disable;
 	bool has_fifo;
 };
 
 struct stm32_uart_info stm32f4_info = {
 	.stm32f4 = true,
 	.uart_enable_bit = 13,
-	.has_overrun_disable = false,
 	.has_fifo = false,
 };
 
 struct stm32_uart_info stm32f7_info = {
 	.uart_enable_bit = 0,
 	.stm32f4 = false,
-	.has_overrun_disable = true,
 	.has_fifo = false,
 };
 
 struct stm32_uart_info stm32h7_info = {
 	.uart_enable_bit = 0,
 	.stm32f4 = false,
-	.has_overrun_disable = true,
 	.has_fifo = true,
 };
 
@@ -62,6 +60,7 @@
 
 #define USART_CR3_OVRDIS		BIT(12)
 
+#define USART_SR_FLAG_ORE		BIT(3)
 #define USART_SR_FLAG_RXNE		BIT(5)
 #define USART_SR_FLAG_TXE		BIT(7)
 
@@ -69,4 +68,5 @@
 #define USART_BRR_M_SHIFT		4
 #define USART_BRR_M_MASK		GENMASK(15, 4)
 
+#define USART_ICR_OREF			BIT(3)
 #endif